• MD5 Hash


    The MD5 Hash Engine is a  block which supports the 512bit block sized algorithm specified within rfc1321.  The deliverable is Verilog (2001) RTL.

    The hierarchy of the design is as illustrated within Fig 1:

    Fig 1: MD5 Hash Engine – RTL Hierarchy

    Port List

    The top level of the design has three key interfaces; Control & Status, Message Stream and Message Digest.  The full signal port list is as tabulated below:

    clk 1 Input Core clock
    resetn 1 Input Active low reset. Asynchronous assertion, synchroponous de-assertion
    message_start 1 Input Calculation start request
    message_length 64 Input Message length (in bits) for processing
    idle 1 Output Calculation processing status indication
    message_data 32 Input Data Word (from message stream)
    message_valid 1 Input Data Word valid indication
    message_enable 1 Output Data Word enable indication
    digest 128 Output Digest Result
    digest_valid 1 Output Digest Result valid indication
    digest_enable 1 Input Digest Result enable indication


    Fig 2 details a typical interface sequence for a hash calculation:

    • From the idle state (i.e. when the idle output is high), the message_length input is sampled when message_start is asserted.
    • Once in the active state (i.e. when the idle output is low), the state of the message_start input is ignored until the module has reached idle again (message_length may also be changed in value during this time).
    • With the module in the active state, the message_enable output is asserted to allow reception of message data over the Message Stream interface.
    • Message data may be presented within a single cycle via a valid /enable handshake protocol.  I.e. when valid data is presented, it is only accepted if the enable output is asserted too.  Fig 2 illustrates how there may be a delay after negation of the idle status before message_valid is asserted – however this is not an interface requirement.  Valid data may be presented earlier – message_enable will only become asserted once the module is active.
    • After the configured length of data for a given message has been received, the message_enable output will be negated and the hash calculation allowed to complete.  Upon completion the resultant Message Digest will be presented for output – again via a valid / enable protocol.
    • After the valid Message Digest has been enabled, the module will return to the idle state (i.e. idle is asserted again) and become ready to accept a new calculation request through a subsequent assertion of message_start.

    Fig 2: Interface Signal Sequencing (Typical)

    Data Alignment

    The Message Length is presented as a 64 bit value, with the MSb in the bit[63] position and the LSb within bit[0].

    The Message Stream data is packed onto the message_data bus as per the MD5 hash specification:

    • The bit stream (from first bit towards last) is split into a series of 8 bit bytes with the earliest bit in the MSb position of each byte.  Bytes are then grouped in 4’s to achieve 32 bit words – with the earliest byte regarded as the LSB (but occupying bits [31:24] of the word) and the most recent byte regarded as the MSB (and occupying bits [7:0] of the word).

    Message streams which complete on a non-aligned data word will be packed into the MSbits of the final 32 bit input word.

    The Message Digest result is ordered as per the MD5 hash specification and packed from the MSB of the 128 bit digest output:

    • the A term is presented (LSB first) in digest bits [127:119] followed by terms B, C and D (completing with the high order Byte of term D within bits [7:0]).